There are conventionally known techniques for improving the arrangement of drivers that drive word lines, control gate lines, or memory gate lines connected to memory cells, or for reducing the number of drivers.
A semiconductor device of Japanese Patent Laying-Open No. 2009-246370 (PTD 1), for example, includes a first driver that drives a control gate line and a second driver that drives a memory gate line. The first driver uses a first voltage as an operating power supply, and the second driver uses a voltage higher than the first voltage as an operating power supply. As such, the first driver is disposed on one side and the second driver is disposed on the other side, with a nonvolatile memory cell array interposed therebetween. It is possible to separate drivers each operated with a high voltage as an operating power supply and circuits each operated with a relatively low voltage as an operating power supply from one another.
A memory cell array of Japanese Patent Laying-Open No. 11-177071 (PTD 2) is divided into a plurality of blocks in the bit line direction, and furthermore, each block is divided into a plurality of sub-blocks in the word line direction. The word lines driven by a word line driving circuit are connected by control transistors formed in boundary regions between the sub-blocks, and are continuously provided to extend over the plurality of sub-blocks. Consequently, simultaneous erasure on a sub-block basis can be performed.